1. Field of the Invention
The present invention relates to a method for manufacturing field effect transistors (FETS) having an extremely short channel with greatly improved punch-through, channel breakdown, and hot electron trapping characteristics.
2. Development of the Invention
It is well known in the art that the speed of a MOSFET is determined primarily by channel length and parasitic capacitance, speed improving as channel length and parasitic capacitance are reduced in value. Reducing channel length decreases transit time between the source and drain while reducing parasitic capacitance decreases charging time.
The most common MOSFETS are those which utilize source and drain regions on the surface of a silicon wafer, the source and drain regions being separated by a channel region with current being controlled by a gate electrode overlying the channel region and insulated therefrom by a thin layer of silicon dioxide (often termed an IGFET).
While such devices are amenable to LSI fabrication techniques, they typically suffer from the drawback that it is difficult to make a short channel and accurately register the gate electrode thereover.
U.S. Pat. No. 4,033,026 Pashley discloses a method for fabricating MOS silicon gate transistors; Pashley does not disclose the essential concepts of the present invention and does not involve the use of a self-aligning gate whose location can be controlled with high accuracy. Further, Pashley does not appear to contemplate any embodiment whereby extremely short channel MOSFETS can be obtained.
U.S. Pat. No. 4,038,107 Marr et al relates to making short channel FETs. The method of Marr et al has the following characteristics:
The boron implant through the polysilicon window 16 into substrate 10 to form P region 17 defines the dopant (boron) concentration in the future channel. Thereafter, a thermal oxidation of polysilicon 15 to grow oxide sidewall 19 whose thickness will define the channel length is conducted. For a channel length, for instance in the range of 0.5 to 1 um, the corresponding oxide 19 thickness should be about the same (0.5 to 1 .mu.m). The thermal oxidation is a high temperature process, and the oxide growth rate decreases rapidly with the growing oxide thickness. During the heating to oxidize polysilicon 15, the polysilicon goes through a grain growth process, which results in a roughened surface texture. Furthermore, the oxidation of silicon is orientation dependent which induces safety asperity. The combined effect of grain growth surface roughening and the orientation surface asperity makes the trace channel length varying along the channel width which can have grave consequence in controlling submicron channel length devices. In contrast, in the present invention the channel length is defined by a second polysilicon layer which can be grown at 600.degree. C., resulting in a very smooth surface and a channel length well defined along the channel width.
Further, in Marr et al FIG. 3 after oxidation of polysilicon 15 to form oxide 19, the oxide on the monosilicon substrate under polysilicon 15 and under the window 16 show the same thickness, which is not possible unless the silicon under window 16 is masked with an oxidation mask such as silicon nitride. While Marr et al do not per se disclose masking the window surface, if there is no oxidation mask in the window area oxide growth must occur simultaneously with polysilicon 15 oxidation and oxide thickness should be comparable to the oxide 19. In subsequent phosphorus implantation, the implanting energy must be very high to penetrate the thick oxide on the monosilicon under window 16 into the substrate silicon to form N region 18. For an oxide thickness of 1 um for a 1 um channel, the phosphorus implant energy has to be about 1,400 kev, nonexistent at any practical semiconductor manufacturer. In contrast, the present invention has no polysilicon oxidation; hence, the source/drain implant only penetrates through a thin gate oxide.
Further, polysilicon 15 and its oxide 19 in FIG. 4A of Marr et al are removed and electrode 24 is formed after the channel length 17 is defined as shown in FIG. 3. Thus, the electrode is not self-aligned with the channel length as shown in FIG. 4A. In contrast, in the present invention channel length is defined by a second polysilicon growth which is an integral part of the device.
In Marr et al the large overlap between electrode 24 and source 18/drain 11 due to nonself-alignment of gate 24 to channel 17 results in a high gate capacity which degrades device performance. In contrast, the present invention has a self-aligned gate to channel and the overlap between the gate electrode and the channel can be controlled to a minimum, e.g., less than 0.1 um. As a result, device performance is enhanced by the low gate capacitance. Further, the source p-n junction of regions 17 and 18 in Marr et al occurs in a high dopant concentration region, resulting in high parasitic capacitance, which degrades device performance. In contrast, in the present invention the source p-n junction occurs in a low substrate background concentration; hence parasitic capacitance is low.
U.S. Pat. No. 4,074,300 Sakai et al discloses a self-aligned silicon gate process. The polysilicon length is defined by a photoresist process and a subsequent etch of the polysilicon. The Sakai et al process suffers from inherent large photoresist variation in the range of a few tenths of a micrometer and the complexity of the variables involved in a silicon etch. The combined variations in photoresist and silicon etch result in large variations in channel length. To make submicrometer channel devices using the Sakai et al method will result in widely varied device characteristics. In contrast, the present invention defines channel length by controlling a simple chemical vapor deposition--second polysilicon thickness--with a variation much less than 0.1 um.
U.S. Pat. No. 4,078,947 Johnson et al deals with a method for forming narrow channel length MOSFETs. While Johnson et al do use the terminology "self-aligned structure", the self-alignment concept in Johnson et al is quite different from that of the present invention, i.e., it is easily seen that in Johnson et al the "self-alignment" of the gate merely reflects the fact that the channel length is determined by the outward diffusion of the implanted boron in region 20 (FIG. 1) and the subsequent n implant or diffusion through the same opening to form region 22. Clearly the channel length 28 per Johnson et al is defined by a diffusion/implant process but not by a first polysilicon mask for implanting boron in region 22a and subsequently by a second polysilicon mask for implanting n-type dopants to form regions 29 and 32a as per the present invention. Since the channel length is formed by the outward diffusion of boron, the surface boron concentration in channel 28 varies along the channel length in Johnson et al. On the other hand, the surface dopant concentration of channel 30 per the present invention is the same along the channel length due to the implantation of uniform concentration in the channel region. Furthermore, the gate electrode of Johnson et al is formed after channel length is defined and electrode 52 is not self-aligned with channel 28, the large overlap between electrode 52 and source 22/drain 24 in Johnson et al resulting in high gate capacitance which degrades device performance.
U.S. Pat. No. 4,099,987 Jambotkar discloses a technique wherein the channel length of an bipolar transistor is controlled by the thickness of a dielectric layer deposited on the vertical walls of a mesa. The mesa and layer are removed, and are replaced by a non self-aligned gate structure.
U.S. Pat. No. 4,101,922 Tihanyi et al relates to FET's having a short channel length. A review of Tihanyi et al establishes that there is little relationship between Tihanyi et al and the present invention, and this reference is merely cited as showing an FET with a short channel length.
U.S. Pat. No. 4,173,818 Bassous et al relates to a method of fabricating transistors, most especially IGFETs having a very short effective channel. The Bassou et al teaching differs from the present invention as follows:
The channel length 34 is defined by the undercut of the tungsten layer 24 in two separate etches as shown in FIGS. 1C and 1D. Undercut etch control is a function of many variables such as tungsten thickness, grain structures, grain orientations, etchant composition--which changes continuously during etching, surface area of tungsten to be etched, etchant temperature, and rate of removal of the etching by-product at the etching tungsten surface.
Tungsten 24 is eventually removed and oversized polysilicon 20 is used as the gate electrode which extends well over the right side end of channel 34 and overlaps with the drain side n- region 16 for several micrometers, thus increasing parasitic drain capacitance which degrades device performance. In contrast, the present invention uses a precisely controlled second polysilicon thickness to define channel length and has a minimum gate to source/drain overlap of less than one-tenth of a micrometer.
The depth of channel 34 at a given implant energy depends upon the thicknesses of the polysilicon 20 and the gate oxide 18 per Bassous et al. Thus, channel depth varies with thickness variations of both the polysilicon and the gate oxide. In contrast, the present invention makes the channel implant through the gate oxide only; hence, channel depth varies with gate oxide variation only.
Per Bassous et al, the large source p-n junction occurs at a dopant concentration much higher than the substrate dopant concentration which results in high junction capacitance, whereas per the present invention the large area source p-n junction occurs at a low substrate dopant concentration.
U.S. Pat. No. 4,190,850 Tihanyi et al differs from the present invention as follows:
The channel length 121 in FIG. 4 of Tihanyi et al is defined by the slope 21 of polysilicon 21 and the gate oxide thickness. The channel length thus varies with variations of the slope and the gate oxide thickness. In contrast, the present invention precisely controls the channel length by the second polysilicon thickness.
The depth of channel 121 changes with slope 31 while the present invention has a constant channel depth.
U.S. Pat. No. 4,209,349 Ho et al differs from the present invention as follows:
In FIG. 2D of Ho et al, the device structure comprises, from source to drain, N.sup.+ 36, P30, P.sup.- 22, P30 and N.sup.+ 36, while the present invention shows a structure per FIG. 5 from source to drain of N.sup.+ 32a and N29, P30, N.sup.-16, N26 and N.sup.+ 32b.
In Ho et al, channel 30 is aligned with the edge of a dielectric sidewall 32 in FIG. 2C which eventually has to be removed and has to be released by a conductive gate electrode. In doing so, the materials above the silicon surface such as sidewall oxide 32, silicon nitride 28, and oxide 26 are all removed, an insulating layer 52 about 3,000-5,000 .ANG. is grown, photoresist masking is conducted to selectively etch windows in region 52 to define the gate, followed by gate oxidation, again using the photoresist mask to define the source and drain contacts by etching windows in 52. Thus, the gate electrode is defined by a photoresist process which is known to have large variations and the gate electrode is not self-aligned with the channel length 30.
Commenting upon the prior art in general, the prior art has used double diffusion process (DDP) or DDP-like processes to form short channel devices. Devices made by such methods have a relatively short "electrically effective channel" but physically a long device channel is still present whether the device gate is made of aluminum or polysilicon. Thus, a large part of the channel serves no useful purpose, rather, it contributes only to parasitic capacitance. In devices formed per the present invention, channel length is defined by a short physical gate and gate to source or drain overlap is minimized, thereby greatly reducing parasitic capacitance.